Key Takeaways

• Voltage sag analysis is most useful when it starts at the sensitive load bus and works back through the network to the fault source.
• Remote faults, source strength, feeder impedance, and clearing time will all shape the retained voltage that equipment actually sees.
• A sag study becomes actionable only when simulated events are checked against device ride through limits and protection timing.

Accurate voltage sag analysis starts at the equipment bus, because a short fault several buses away will still depress voltage enough to trip sensitive loads.

That reach matters because the annual cost of power interruptions to U.S. customers was estimated at US$22.8 billion to US$188.0 billion, with commercial and industrial users carrying much of the loss. A plant does not need to be faulted to lose a batch, stop a conveyor, or drop a contactor. You will get the right answer only when the network fault and the equipment ride through limit are studied as one problem. You will miss that exposure if you screen events only at the service entrance. That is the practical value of voltage sag analysis.

Voltage sag starts with fault current through system impedance

A voltage sag happens when fault current flows through the source and network impedance between the supply and your bus. The larger that current path voltage drop becomes, the lower the retained voltage at the load bus will be. Sag depth is a network response, not a mystery at the process end.

A simple feeder example makes this clear. A three-phase short on an upstream bus pulls heavy current from the utility source, and the voltage at nearby buses falls until protection clears the fault. Your motor control centre can see 0.7 per unit voltage even when no device inside the plant has failed. That dip comes from system impedance, fault type, and source strength acting at the same time.

This matters because many teams still treat a voltage sag as a local load issue. It is usually a system issue first. Once you frame it that way, the model needs accurate source data, line impedance, transformer impedance, and fault parameters before you look at the process load. Protection timing will also shape how long the process sees the dip.

Remote faults can still depress voltage at sensitive buses

A fault does not need to sit on your feeder to cause a harmful voltage sag. Remote transmission or subtransmission faults will transfer through the network and depress voltage at a sensitive bus for a short period. Distance reduces the effect, but it does not remove it.

A common plant case is a fault on a neighbouring utility line that clears in 120 ms. The service bus might only drop to 0.82 per unit, which looks mild on a utility plot, yet that same event will open a weak control relay or trip a variable speed drive undervoltage function.

“The cost shows up at the process, not at the faulted line.”

You should treat remote fault exposure as part of normal system performance. Engineers who study only on site faults will miss a large share of nuisance trips. Voltage sag analysis is useful because it ties a distant network event to the exact retained voltage seen where production stops. That link is what turns a utility disturbance into a plant reliability problem.

Start voltage sag analysis at the point of use

The best place to start voltage sag analysis is the bus feeding the device that must stay on. You need the equipment voltage tolerance first, then you work outward through transformers, feeders, and source data. If you start at the fault location, you will miss the actual ride-through question.

You’re usually trying to answer a narrow engineering question, and the input set should stay focused on that bus:

• Nominal voltage at the protected load bus
• Transformer data between the source and the load
• Feeder impedance for each cable or line segment
• Fault locations and fault types worth testing
• Ride-through limits for the sensitive device

A packaging line gives a good example. The line does not fail because the service entrance dipped. It fails because a control power supply dropped out at 480 V for 90 ms. Once you anchor the study at that bus, every model choice becomes clearer and the results will match the operating question you’re trying to answer.

Source strength sets how deep the sag will be

Source strength will largely determine how far the voltage drops during a fault. A stiff source with high short circuit capacity holds voltage better, while a weak source collapses faster under the same fault. Two feeders with the same fault current path can produce very different retained voltage.

Consider a plant served from a strong utility grid and the same plant served from a smaller islanded generation source. A fault on a downstream feeder will produce a shallower sag in the first case and a deeper sag in the second, even if the line lengths and transformer sizes stay unchanged. Short circuit level is the first screening value you should ask for.

This is why generic voltage dip assumptions are risky. A fixed 20% dip estimate will mislead you on both strong and weak systems. Good modelling turns source data into a retained voltage result at the bus that matters, which is what equipment checks actually need. You’ll get better results when the model uses the utility short circuit level instead of a placeholder source.

Feeder impedance shapes the sag seen by downstream loads

Feeder impedance will shape the sag profile across a plant or utility circuit. Long runs, smaller conductors, transformer steps, and large motor buses all alter how much of the upstream disturbance reaches a downstream load. One fault will not look the same at every bus.

A long 4.16 kV feeder feeding remote pumps will often show a deeper dip at the motor starter bus than at the main switchgear. Another case appears on a feeder with several transformer stages, where the retained voltage at a low voltage control panel drops below a relay threshold even though the medium voltage bus stays acceptable. Feeder detail decides which buses are safe and which are exposed.

That spread across buses is why site-wide averages do not help much. You need bus-specific results. Simulate voltage dips on a feeder with enough electrical detail to keep those differences visible, or the weak point will stay hidden. That extra resolution is often what exposes the vulnerable control bus.

Fault clearing time sets equipment ride-through risk

Fault clearing time decides how long the load must survive at reduced voltage. Depth matters, but duration often separates a harmless sag from a process trip. A shallow dip that lasts too long will still defeat contactors, DC power supplies, and drive controls.

The ride-through check needs an actual time pair, not a single voltage number. The ITI curve shows this clearly, with 70% retained voltage tolerated for only 0.5 s and 80% retained voltage for 10 s. A feeder breaker that clears in 80 ms will produce a very different process outcome than backup protection that clears in 600 ms.

A control system trip often starts with small devices, not the large motor everyone is watching. A relay coil, 24 V power supply, or process controller usually won’t forgive the longer event. That is why voltage sag analysis steps must keep protection timing and equipment tolerance on the same plot. You’re checking the full sag duration against device survival limits.

Feeder studies need faults placed along the full circuit

A useful feeder study will place faults at multiple points along the circuit and will test the fault types that the feeder can actually experience. Single-line to ground, line to line, and three-phase faults produce different retained voltages at each bus. One test point will not represent the full feeder.

A lateral fault near the feeder end can expose one remote process area while leaving another nearly untouched. A main feeder fault closer to the source will depress more buses at once, but the retained voltage at each load still depends on the local impedance path. That is why engineers build a fault set instead of relying on a single worst-case guess.

SPS fits this stage well because you can place faults across buses and line sections, keep the source and feeder model transparent, and compare retained voltage at the exact loads you care about. That kind of open model matters when you’re checking assumptions with protection staff, operations teams, or students in a lab.

Ride through checks turn sag results into design action

Ride through checks convert a voltage sag plot into a clear engineering judgement about what will stay online and what will trip. That judgement needs the retained voltage, the event duration, and the actual tolerance of each sensitive device. Once those three line up, you can act with confidence.

A useful check is often simple. Match the simulated sag at the process bus against the undervoltage trip setting of a drive, the dropout curve of a contactor, or the hold-up time of a control power supply. You’ll see quickly if the weak point is the network, the protection timing, or the equipment setting. That check also keeps mitigation spending tied to the actual failure point. That is where model results stop being academic and start guiding plant fixes.

Good practice is disciplined rather than flashy.

“You place faults where they can occur, model the path the sag will take, and test the load that must survive.”

SPS SOFTWARE supports that workflow well because the value sits in clear system behaviour, visible assumptions, and checks that match the events your equipment will actually face.

Key Takeaways

• Capacitor bank switching overvoltage is set by the first milliseconds of the close, so time-domain study is required.
• Back to back bank arrangements and breaker behaviour often create the highest stress cases in a switching study.
• Mitigation only counts when waveform checks show lower peaks at every bus that hosts sensitive loads.

Capacitor bank switching must be studied as a transient event, because a routine close can create overvoltage that reaches far beyond the switched bus.

Steady-state reactive power checks won’t show the first peak, the inrush path, or the way nearby banks reflect the event back into the feeder. A Lawrence Berkeley National Laboratory study estimated that power disturbances cost U.S. businesses $104 billion to $164 billion each year, which gives short switching events practical weight beyond the waveform screen.

Capacitor bank energization creates steep transient overvoltage

Closing a capacitor bank connects an uncharged element to a live network, so the first milliseconds are set by the voltage difference, source inductance, and breaker timing.

“Steady-state reactive power calculations won’t reveal it.”

A 13.8 kV industrial bus can look calm in load flow, yet the same bus can ring sharply when a 2.4 Mvar bank closes near a lightly damped source. Sensitive power supplies respond to the peak rather than the reactive support. The ITIC voltage tolerance curve places 120% of nominal voltage outside the normal operating region once it lasts more than 0.5 cycle, which shows why a brief rise still matters when it reaches control circuits or drive front ends.

You need capacitor bank switching transient simulation because the damaging part of the event happens before the bank settles to its new steady voltage. Cable length, transformer leakage, and local load impedance all shape that first oscillation. If you only inspect the bus after the breaker is fully closed, you’ll miss the event that trips equipment.

Back-to-back banks magnify the first peak

Back-to-back switching is severe because an energized bank will discharge into the newly closed bank through very low inductance. That local exchange creates higher inrush current, higher frequency oscillation, and stronger voltage magnification than a single isolated bank energization case.

A common plant arrangement makes this easy to miss. One bank is already on the bus, a second bank closes for added reactive support, and the current path between them is only the short buswork and breaker connection. That path has little resistance, so the first current crest rises fast. Protection that never reacts to a remote feeder fault can still see sharp current spikes during this close.

Voltage magnification also appears away from the switched bus. A nearby motor control centre, a long cable to a variable speed drive, or a tertiary winding on a transformer can show a larger crest than the capacitor terminals themselves. That is why a capacitor bank switching study has to include adjacent buses and connected equipment, not only the bank that is being energized.

EMT simulation captures capacitor switching transients in time

EMT simulation captures capacitor switching transients because it resolves the waveform sample by sample through the switching instant. You can see the first peak, the oscillation frequency, the decay rate, and the way reflections move through feeders, transformers, and nearby capacitor banks.

A practical case study starts with the pre-switch steady state, then closes the breaker at defined angles across several runs. You’ll usually record bus voltage, capacitor current, breaker current, and the voltage seen by nearby loads. A 60 Hz phasor study cannot show the difference between a mild ring and a steep surge at a drive bus, but an EMT run will show it clearly.

That time view also helps you separate causes. One case might be dominated by local bus inductance, while another is set by a long cable reflection or a transformer capacitance path. When you model capacitor bank energization this way, mitigation moves from guesswork to direct comparison of waveforms, current peaks, and damping time.

A useful EMT model starts with stray inductance

Useful capacitor switching modelling starts with the inductance and resistance that sit between the source, breaker, bus, and capacitor bank. Those small elements set the inrush frequency and peak current, so an ideal source tied to an ideal capacitor will give a neat waveform that is physically wrong.

A short section of bus duct, a few metres of cable, or a small current-limiting reactor can change the shape of the event more than a large shift in steady-state load. A transparent model in SPS SOFTWARE lets you inspect those paths directly, which matters when you are checking why two similar banks produce very different switching records on site.

That level of detail does not make the study complicated for its own sake. It makes the result believable. You’re not trying to build every screw and bracket, but you’re trying to capture the electrical path that will shape the transient overvoltage and the inrush current seen by the breaker.

Breaker closing angle controls the worst energization case

Breaker closing angle matters because the voltage difference across the contacts at the instant of conduction sets the first charging surge. The worst case appears when the trapped capacitor voltage and source voltage create the largest mismatch at contact touch or prestrike.

A three-phase bank closing near a source voltage crest will not produce the same stress as a close near a zero crossing. Phase spread makes this more severe, because poles do not close at the exact same microsecond. One feeder can show a modest phase A peak and a much larger phase C peak simply because the pole timing and trapped charge line up badly.

You should treat closing angle as a sweep, not as a single run. A useful set of cases includes several point-on-wave positions and trapped voltage states after previous de-energization. That approach will show the true upper bound of the event, which is the value that matters when you are checking insulation margins and load ride-through.

Switch models must represent prestrike restrike behaviour

Switch models must represent prestrike and restrike because real interrupters do not always move from open to fully closed in one ideal step. Contact approach, dielectric breakdown, and current interruption can create extra voltage steps that raise stress above the clean close shown by an ideal switch.

Vacuum and air interrupters can show very different signatures during capacitor switching. A bank that looks acceptable with an ideal breaker can produce a harsher waveform once prestrike is added, because the capacitor starts to charge before mechanical contact seals. Another case can show restrike during opening, which means the study should not stop at energization if field records show complaints during both close and trip operations.

This matters most when you are testing protection pickups, surge arrester duty, or insulation coordination margins. An ideal switch is still useful for screening, but final settings and final mitigation checks need the switch behaviour that matches the breaker technology installed in the yard.

Mitigation should be tested at every affected bus

Mitigation works only when it reduces the crest and ringing at the buses that actually host sensitive equipment. A fix that looks good at the capacitor terminals can still leave a higher peak at a drive bus, transformer tertiary, or remote control panel.

A typical industrial feeder shows this clearly. A reactor at the bank may cut local inrush current well, yet a long cable to a process line can still see reflected overvoltage if the switching sequence is poor. You should test each measure at all affected observation points, then compare the worst remaining crest, oscillation frequency, and decay.

• Current limiting reactors reduce peak inrush current and shift the oscillation to a lower frequency.
• Controlled closing narrows the range of breaker angles that produce the highest stress.
• Switching order matters when one energized bank can feed the next close through a short bus path.
• Surge arresters should be checked at the buses where reflected peaks actually appear.
• Damping elements must be sized from waveform results rather than from steady-state ratings alone.

That process answers the common question of how to reduce switching overvoltage with evidence instead of habit. You’re checking the full surge path from source to affected bus.

Study results should guide switching timing policy

A capacitor bank switching study earns its value when results become operating rules for timing, sequencing, and permitted system states.

“Good policy comes from the worst verified waveform, the buses that saw the highest stress, and the mitigation that held those values inside acceptable limits.”

One utility feeder may need a rule that blocks a second bank close until the first bank is settled and a reactor is in service. Another plant may need a fixed sequence that keeps a long cable bus off line during capacitor energization. Those rules are simple, but they only stay credible when they come from waveform evidence instead of a generic switching note.

That is where a disciplined model pays off. SPS SOFTWARE fits this work because you can trace the physical path of the transient, inspect the assumptions, and turn a capacitor bank switching study into a clear operating practice that keeps routine switching from becoming a recurring source of trips.

Key Takeaways

• STATCOM sizing will be accurate only when the target is tied to a disturbance and a voltage recovery requirement.
• Weak-grid studies should centre on short-circuit strength, control limits, and post-fault recovery instead of steady state MVAr alone.
• Transparent FACTS models give you a defensible path from initial compensation estimates to final control settings.

Reactive power compensation should be sized against disturbance duty, not only steady-state MVAr.

Steady state studies will tell you how much reactive support a bus needs at one operating point, but they won’t tell you if the device can hold voltage through a fault, a plant ramp, or a control interaction. That gap matters more now because renewable capacity additions reached almost 510 GW in 2023, with solar photovoltaic leading the increase. More inverter-based connections mean more sites where voltage support must be checked in motion, not as a single snapshot.

“A good STATCOM study starts from the disturbance you expect the grid to survive and works back to the current, control limits, and recovery target you need.”

That approach gives you a compensation rating tied to voltage behaviour, fault ride through, and plant control interactions. It also gives you a model you can trust when the grid is weak and the margin for error is small.

FACTS devices support voltage control in stressed networks

FACTS devices are used to control voltage, reactive power flow, and transfer capability when the network cannot hold acceptable voltage on its own. A STATCOM is one member of that group, and it is often selected when the grid is weak, the voltage swings are steep, or the response must stay effective during a disturbance.

A long collector system feeding a remote substation is a clear example. The bus can sit within limits at normal output, then fall sharply when a nearby fault is cleared or when a large motor starts. A fixed capacitor will only supply a fixed amount of reactive power, and an on-load tap changer will move too slowly. A controlled shunt device can react on the timescale that the voltage problem appears.

You should treat the device class as a control function first and an MVAr nameplate second. That framing keeps you focused on the reason the equipment is being installed. If the site problem is post-fault voltage recovery, the useful comparison is response quality under stress, not only the steady state reactive requirement at rated voltage.

STATCOM sizing starts with the voltage control target

A STATCOM should be sized from a voltage target tied to a specific operating event. You need to define the bus, the acceptable minimum voltage, the duration of the dip, and the recovery time. Those values turn a vague reactive requirement into a current and control problem you can actually test.

A point of interconnection at 132 kV shows the method well. If your plant must hold the bus above 0.92 pu during a three-phase fault recovery and return to 0.98 pu within a few hundred milliseconds, the STATCOM rating has to support that path. A load flow result that says the bus needs 35 MVAr at nominal conditions does not answer that operating target.

You’ll also need to decide what is being protected. Some projects are built around a grid code voltage envelope. Others are built around feeder motor performance, converter stability, or plant controller margins. Once the target is explicit, the rating study becomes disciplined. Without that target, the chosen size will reflect convenience more than system behaviour.

Weak grid strength sets the useful MVAr range

Grid strength sets how much benefit each extra MVAr will actually deliver. A weak grid will show large voltage movement for a modest current injection, but it will also expose control interaction, current saturation, and poor recovery if the device is undersized. Useful sizing comes from the system short-circuit level, not only the reactive requirement.

Connections based on inverter-heavy generation make this more common. Solar and battery storage account for 81% of new U.S. utility-scale generating capacity expected in 2024. A site with low short-circuit strength and a long export line will often need a STATCOM sized for fault recovery current, even if the normal reactive requirement looks modest.

A wind or solar plant tied into a remote bus can illustrate the trap. The bus may regulate well at 20 MVAr during normal export, yet need 60 MVAr worth of controlled current support once a fault is cleared and converter controls re-synchronise. That is why weak-grid studies should treat short-circuit strength as the main sizing frame, then refine the range with operating cases.

Control limits shape the STATCOM dynamic response

The STATCOM dynamic response is shaped by current limits, control gains, voltage measurement filtering, and protection thresholds. Those elements decide how much reactive current is actually available during a dip and how cleanly the device returns to normal control after the event. Nameplate MVAr alone will not tell you that behaviour.

A practical case is a controller tuned for very tight voltage regulation on a bus with noisy measurements. If the filter is too light, the converter can chase small voltage swings and hit its current ceiling before the severe event arrives. If the filter is too heavy, the response comes late and the bus falls deeper than expected. Both cases can happen with the same MVAr rating.

You should also check the control priority during current saturation. Some models prioritise reactive current first, while others share current between active and reactive components. That choice matters at renewable interconnections where plant-level controls are also acting. A clean study records the current ceiling, the voltage regulator limits, and the recovery logic so you can see what the converter will actually do.

Simulation should reproduce the full disturbance sequence

Reactive power compensation simulation should reproduce the full event sequence from pre-fault conditions to post-fault recovery. A useful model includes the network, the device controls, the plant controls, and the switching actions that occur around the disturbance. If one piece is missing, the voltage result will look cleaner than the site will.

A fault on a nearby line is a simple example. The bus voltage drops, the STATCOM pushes reactive current, breakers clear the fault, plant converters recover, and tap changers or capacitor steps react later. A model built in SPS SOFTWARE lets you inspect each controller and test that sequence with transparent parameters instead of hiding the behaviour inside a black box.

• Pre-fault operating point at the studied export or import level
• Fault type, duration, and clearing order at the correct buses
• Current limits and protection thresholds inside the device controls
• Plant or feeder controls that react during recovery
• Post-fault voltage recovery criteria that match the project requirement

If you can’t reproduce the sequence, you can’t trust the rating. The most common sizing errors appear after the fault is gone, when devices hit limits, controls interact, and voltage takes longer to recover than the steady state study suggested

STATCOM versus SVC under deep voltage dips

The main difference between a STATCOM and an SVC is how well reactive support holds up as voltage falls. A STATCOM is current-based, so it keeps stronger support at low voltage. An SVC depends more heavily on system voltage, so its effective reactive output drops more sharply during deep dips.

A transmission bus exposed to severe fault dips shows the contrast clearly. The SVC can regulate well during normal operation and mild disturbances, yet it loses strength when the voltage falls to the point where support is needed most. The STATCOM usually gives you better low-voltage support and cleaner recovery, though its converter controls still need proper tuning and current limits.

Load flow snapshots miss the worst compensation duty

Load flow snapshots miss the worst compensation duty because they solve a settled operating point after transients are gone. They are useful for initial screening, bus placement, and normal operating range, but they will not show current saturation, control interaction, or delayed voltage recovery during a disturbance.

A collector station can make this obvious. The steady-state case might show a 25 MVAr shortage at peak export, which suggests a modest device rating. The fault study can show the bus needs the equivalent of 70 MVAr worth of reactive current support for a short interval to stay above the plant trip threshold. Both results are true, but they describe different duties.

“You should use load flow to frame the starting point, then let disturbance studies set the final size.”

That order prevents a common mistake: selecting compensation from a tidy bus voltage report and finding later that the device can’t hold the bus through the event that actually matters.

Transparent control models improve confidence in final settings

Transparent control models improve confidence because you can see how the compensation will behave before you commit to final settings. That visibility matters more than another decimal place in the steady state result. Final tuning depends on filters, limits, and recovery logic that need inspection, not assumption.

A utility interconnection study often passes through several revisions as fault levels, export limits, and plant controls are updated. Open models let you adjust the voltage regulator, current ceiling, or measurement filter and check the effect without losing track of the physical meaning. That is why engineers working in SPS SOFTWARE can test compensation against disturbance behaviour instead of trusting a single load flow snapshot.

You’ll make better settings when the model tells you why the voltage recovers cleanly or why it doesn’t. A final rating chosen that way is easier to defend in design review and easier to teach to the next engineer who inherits the study. SPS SOFTWARE fits that closing step well because the model stays visible, editable, and tied to the system behaviour you’re trying to control.

Key Takeaways

• Harmonic resonance is a network impedance problem, so device level harmonic limits never tell you enough on their own.
• Frequency scans find where the grid is sensitive, and time domain checks show which switching or control events will excite that sensitivity.
• Careful model detail at weak buses will do more for study quality than broad assumptions across the full network.

Harmonic resonance studies will show you where a grid will magnify distortion before a routine equipment addition turns a small harmonic source into a serious voltage problem.

Utilities and plant engineers keep adding converter-based generation, drives, and reactive support because the grid needs stable voltage and efficient power flow. Resonance risk rises with that mix, since each filter, cable, transformer, and capacitor shifts the network impedance seen by harmonic currents. Renewable capacity additions reached almost 560 GW in 2023, up 64% from 2022, which shows how quickly inverter-based equipment is being added to power systems. A study plan that combines frequency scans with time domain checks will show you the resonant points before equipment insulation, protection, or control performance is affected.

Harmonic resonance occurs when network impedance peaks sharply

Harmonic resonance happens when inductive and capacitive elements line up at a frequency where network impedance rises sharply, so a small harmonic current creates a much larger voltage distortion. You’ll see the problem as amplification of specific frequencies, and that distinction matters when you assess risk.

A 13.8 kV feeder with a capacitor bank, transformer leakage reactance, and several long cables can resonate near the 5th or 7th harmonic. A modest current from a variable speed drive or solar inverter will then produce bus voltage distortion that looks out of proportion to the source. Operators often blame the nearest device alone, even though the grid impedance is doing most of the amplification. Your study has to focus on the full network shape and the emitter that excites it.

That focus will keep you from chasing the wrong fix. Swapping one inverter controller or tightening a distortion limit will not solve a resonance tied to feeder capacitance and source strength. You need the resonant frequency, the impedance peak, and the bus location where the response is worst. Once those are known, mitigation becomes an engineering exercise instead of trial and error.

Inverters shift resonant points through controls filter design

Inverters shift resonant points because their filters, transformer connections, cable lengths, and control loops alter the frequency-dependent impedance of the grid. A bus that looked benign before a plant expansion will resonate after the added equipment changes that impedance map, even if each inverter still meets its individual harmonic limits.

Solar, storage, and wind made up 95% of the 2,600 GW waiting in United States interconnection queues at the end of 2023. That scale matters because queued projects add more converters, more collector cables, and more reactive equipment to the same network. A 100 MW plant expansion often adds enough filter capacitance to shift an existing resonance from one harmonic order to another. Your study should treat every large inverter addition as a network change, not a simple replacement.

Controls add another layer. A grid-following inverter with an LCL filter will interact differently from a plant using different damping values or a different phase-locked loop bandwidth. Two sites built from similar single line diagrams can produce very different scan results once those parameters are included. That’s why simplified generic inverter blocks often miss the frequencies that later show up during commissioning.

Capacitor banks can amplify distortion at specific frequencies

Capacitor banks amplify distortion when their reactance combines with system inductance at a frequency near existing harmonic content. The bank itself does not create the harmonic source, yet it can set the condition that turns a tolerable current injection into damaging bus voltage, relay nuisance operation, or repeated capacitor stress.

A 34.5 kV station with switched capacitor banks can behave very differently before and after a bank closes. The bus voltage may stay within limits at fundamental frequency while the 7th harmonic rises sharply after the switching step. Engineers sometimes see the distortion event and assume a control fault in the nearest inverter. The stronger explanation is often a shifted parallel resonance created by the bank.

This is why capacitor studies need more than kvar sizing. Detuning reactors, bank location, and switching sequence will all affect where the peak lands. Industrial plants with power factor correction face the same issue as renewable collector systems, especially when background harmonics already exist upstream. You’ll get better results when capacitor planning and harmonic studies happen as one task rather than separate reviews.

Frequency scans show where small sources create large voltages

“A frequency scan maps system impedance against frequency, and the peaks tell you where a modest harmonic current will create a large voltage response.”

It is the fastest way to find resonance risk before commissioning, because it shows both the resonant frequency and the bus where the network is most sensitive.

A plant interconnection study often scans from the point of common coupling down to inverter terminals and auxiliary buses. One bus may show a mild response at the 5th harmonic while a collector bus shows a steep peak near the 11th. That contrast tells you where to place filters, where to shift capacitor settings, or where more model detail is needed. A scan will also show when a new cable run moves the peak enough to matter.

Time domain studies confirm resonance under switching events

Time domain studies test resonance under switching and control events that a scan cannot show on its own. They will confirm if a resonant point actually produces harmful overvoltages, sustained ringing, or current stress when a capacitor closes, an inverter ramps, or a fault is cleared.

A capacitor energization event at a weak bus can excite a resonant frequency for several cycles, even when steady-state harmonic injection looks small. An inverter trip and reclose sequence can do the same if DC link controls and plant-level reactive control re-enter with the wrong timing. SPS SOFTWARE is useful here because you can pair a frequency scan with a transparent time domain model and test the same network under switching events. That link between scan results and waveform response is what turns suspicion into proof.

This step matters because not every scan peak becomes an operating problem. Some peaks sit near frequencies with no meaningful source, while others line up with switching patterns, converter sidebands, or background distortion already present on the feeder. You’ll make better mitigation choices when you know the event that excites the resonance, the duration of the response, and the devices that see the highest stress. That evidence also helps protection and operations teams agree on settings and switching rules.

Model detail determines which resonant peaks appear

Model detail decides which resonant peaks you will find, because resonance is set by the actual inductance, capacitance, resistance, and controls present in the network. A study that lumps cables, omits transformer winding data, or treats filters as generic blocks will shift or erase peaks that exist on the site.

A collector system with several 2 km cable segments behaves differently from the same plant modelled as one equivalent line. Each segment adds distributed capacitance and modifies the local impedance seen from nearby buses. Transformer grounding, winding connection, and stray capacitance also affect zero-sequence and high-frequency response. Those details are tedious, but the missing data will usually hurt the study more than an imperfect load estimate.

You don’t need infinite complexity. You need enough fidelity at the frequencies of concern and at the buses where distortion will be measured or equipment will trip. Good harmonic analysis software is most useful when the model is transparent about assumptions, so engineers can edit parameters, rerun cases, and understand why a peak moves after a design change. That approach is more useful than a closed black box that gives a plot without revealing the network physics.

Study the weakest buses before adding new devices

The weakest buses deserve attention first because they combine low short circuit strength with equipment that shifts impedance. These are the buses where added inverters, capacitor banks, or long cable runs will produce the biggest resonance swings, and where mitigation choices will have the largest effect on the whole system.

A study plan works best when you rank buses before you model every corner of the grid. A point of common coupling may look like the obvious first target, yet the more sensitive location is often a collector bus, an auxiliary medium voltage bus, or a capacitor bank terminal. One industrial feeder can stay quiet at the utility interface while a motor control bus sees severe local amplification. These are the places most teams should check first:

• The collector bus that ties many inverter blocks through long cables deserves an early scan.
• The bus where a switched capacitor bank or filter connects needs separate operating cases.
• The weakest feeder seen by the lowest short circuit ratio should be ranked near the top.
• The low voltage side of a transformer feeding dense power electronics often hides local peaks.
• The remote end of a long cable run with light local load can show sharp impedance swings.

This ranking will save time and improve the first pass of your model. It also keeps you from spending days refining buses that cannot excite or magnify the frequencies you care about. Once the high-risk buses are understood, you can expand the scan set and test contingencies with much better focus. Your mitigation plan will then reflect the actual weak points instead of the simplest single line location.

Common modelling errors hide resonance until equipment trips

Common modelling errors hide resonance because they flatten the impedance curve or place peaks at the wrong frequency. The usual culprits are equivalent cables, missing capacitor states, generic inverter filters, stale utility source data, and cases that stop at a scan without checking the operating event that excites the peak.

One site can pass a preliminary study and still trip capacitor protection after energization because the model used nominal source strength and ignored an alternate feeder configuration. Another site can appear unsafe on paper until the engineer adds the damping resistor that was present in the actual filter bank.

“Good harmonic work is less about software features and more about model discipline, because missing one cable section or mistuning one filter can erase the very peak that later trips equipment.”

You’re judging a physical system, so the model has to stay close to the physical system.

That is the standard you should hold for every harmonic resonance study. A solid workflow pairs frequency scans with time domain checks, updates the model after each design revision, and tests the buses most likely to amplify distortion. SPS SOFTWARE fits that workflow because it supports transparent modelling and lets engineers verify resonance risk before equipment is exposed to avoidable stress. Careful execution will always beat guesswork when resonant points move each time a grid adds new inverters or capacitor banks.