Key Takeaways
- A CCM boost PFC stage works best when you set the current waveform target first and size the inductor, sensor, and loops from that requirement.
- Low-line ripple current is the anchor for inductor selection because it sets the hardest condition for maintaining continuous current and clean sensing.
- Simulation has value only when the sensing path and control path are part of the model, since waveform distortion often comes from those links rather than from the power stage alone.
Continuous conduction mode boost PFC works when the inductor ripple, current sensor, and control loop are sized from the input current shape backward.
Poorly sized boost PFC stages can still reach the bus voltage and still fail the line current target because the waveform was never the design anchor. A single-phase CCM boost front end must pull a near-sinusoidal current from a rectified mains source while keeping the switch, diode, inductor, and control loop inside sane stress limits. Global electricity demand grew by 2.2% in 2023, which keeps front-end efficiency and current quality worth careful engineering. You’ll get a better boost converter design when every component choice is checked against the current waveform it will produce.
Continuous conduction mode defines current flow across each switching cycle
Continuous conduction mode means the boost inductor current never falls to zero during a switching period. That single condition changes the whole power factor correction circuit, because the current loop sees a nearly continuous ramp instead of isolated current packets. You’re controlling an average current shape while the inductor current stays continuous from cycle to cycle. That makes CCM the usual choice for medium and higher power boost converter circuit designs.
A 500 W universal-input stage shows the difference clearly. At 100 kHz, a properly sized inductor will carry a triangular ripple around a rising and falling line-frequency envelope, so the current waveform stays connected from one switching cycle to the next. That continuity reduces peak current compared with discontinuous operation, which lowers switch stress and often improves conducted emissions margins. The tradeoff is control complexity, because current sensing and loop compensation must follow a small ripple riding on a much larger sinusoidal command.
Power factor correction starts with the input current target
Power factor correction starts with the current you want from the mains, not with the output capacitor or duty cycle. A CCM boost PFC stage should make input current follow the rectified input voltage after scaling for power. That means the target waveform is sinusoidal in shape and proportional to instantaneous line voltage. Once that target is clear, the rest of the boost converter design has a fixed job.
A 300 W supply on 230 Vac helps make this concrete. If the rectified line voltage is high, the commanded inductor current must rise in step so the input looks resistive to the source; if the line voltage falls near the zero crossing, the commanded current must also fall smoothly. ENERGY STAR computer power supplies rated at 75 W or higher set a power factor requirement of at least 0.90 at 100% of rated output. If your current reference is wrong, no later tuning step will recover a clean input waveform.
Output voltage choice sets the boost converter operating window
The output voltage sets duty cycle range, semiconductor stress, hold-up margin, and line current stress across the full mains span. A bus that is too low forces high duty cycle near low line, which pushes RMS current up. A bus that is too high raises switch voltage stress and makes efficiency harder to keep. You should choose the bus voltage before final magnetic sizing.
A common design uses a bus around 380 V to 400 V for universal input operation. That choice gives headroom above the rectified high-line peak while keeping switch and diode ratings practical. Push the bus toward 450 V and device loss and insulation margin tighten. Drop near 340 V and low-line duty cycle rises, which makes ripple control harder.
| Bus voltage choice | What it does to the CCM boost stage |
| Bus close to the high-line peak | Duty cycle collapses at high line and headroom disappears, which makes regulation fragile during line sag. |
| Bus near 380 V to 400 V | This range usually balances universal input operation, practical device ratings, and reasonable duty cycle at low line. |
| Bus pushed much higher | Switch voltage stress, output capacitor stress, and switching loss all rise even if current shaping stays acceptable. |
| Bus set too low | Low-line RMS current climbs and the inductor must work harder to keep ripple within a useful CCM range. |
| Bus chosen before magnetic design | This locks the duty-cycle window early, so inductor and sensor choices can be checked against the same current envelope. |
Inductor value comes from ripple current at low line
The inductor in a CCM boost stage is set by allowable ripple current at the worst operating point, which is usually low line and full load. That point creates the largest duty cycle and the highest average input current. A useful design flow starts with a ripple fraction target, then solves for inductance from switching frequency and low-line voltage. You are sizing for current shape first and copper loss second.
A practical case makes the method clear. Take 90 Vac input, 390 V output, 500 W, and 100 kHz switching, then set ripple near 20% to 40% of peak line current as a first pass. The usual on-time ripple relation gives an inductance that keeps switching ripple small enough for continuous current without forcing an oversized magnetic part. High ripple increases zero-crossing distortion and sensor noise. Very low ripple increases volume, cost, and slows transient response.
Current sensing must match the CCM inductor waveform
Current sensing in a CCM PFC stage must measure the waveform the controller actually needs, which is the inductor current or a clean equivalent of it. The sensor must survive switching noise, preserve slope, and stay linear across the full line cycle. You can’t choose the sensor after the power stage is finished, because its limits shape the current loop. Sensor placement belongs in the boost converter circuit and has to be designed with it.
A low-side shunt under the switch gives a simple signal, but the waveform arrives with sharp edges and blanking needs. An inductor DCR network can reduce dissipation, yet temperature drift and filtering delay must be handled carefully or the loop will chase a delayed current estimate. A model in SPS SOFTWARE is useful here because the current sensor, filter, and PWM blanking can be attached to the same inductor waveform you sized. That makes it obvious when a neat sensing schematic is actually corrupting the current information that CCM control depends on.
“Sensor placement belongs in the boost converter circuit and has to be designed with it.”
The current loop must track the rectified sinusoid
The current loop in a CCM boost PFC stage must force average inductor current to follow a rectified sinusoidal reference throughout the mains cycle. Good tracking keeps power factor high and total harmonic distortion low. The loop must be fast enough to correct switching-scale errors and slow enough to ignore noise spikes. You’re shaping a waveform, so bandwidth and filtering have to serve that single job.
A multiplier-based controller gives a clear example. The outer voltage loop sets the power level, the rectified line voltage supplies the shape, and the inner current loop makes the sensed current follow that command every switching cycle. If the current compensator is too slow, crest flattening appears near the top of the line cycle and line current starts to lag the command. If the compensator is too aggressive, switching ripple leaks into the duty cycle and the current waveform becomes ragged. Good tuning shows up as a smooth sinusoidal envelope with only a controlled triangular ripple on top.
Voltage loop bandwidth must stay below line frequency
The voltage loop in a single-phase boost PFC stage must be much slower than the mains waveform so it does not react to twice-line-frequency power pulsation. A fast voltage loop will inject distortion into the current reference and ruin power factor. A slow loop keeps output voltage regulation stable while letting the current loop do its job. This is one of the main limits that separates a working CCM design from a noisy one.
A 60 Hz supply puts a 120 Hz power ripple into the DC bus, even when the current shaping is excellent. If the voltage loop crossover creeps toward that ripple, the controller starts correcting a normal energy swing as if it were an error, and the result is visible current distortion near each half-cycle crest. Many designers keep the voltage loop well below 20 Hz for this reason. The output capacitor, load step target, and hold-up requirement still matter, but they must be weighed against the need to keep the current command free from line-frequency ripple content.
“Good PFC design is less about isolated equations and more about keeping every choice honest against current shape.”
Simulation should expose current distortion before hardware selection
A good simulation of a boost converter circuit will show current shape, ripple, duty cycle range, and sensor limits before hardware is chosen. That check is more useful than a neat schematic because CCM success depends on waveform quality under low line, high line, light load, and full load. You’ll catch weak component choices early if the model includes the control path. That is where disciplined design usually saves time.
A useful review model should check these five points before parts are locked:
- Low-line ripple stays inside the intended CCM range.
- Sensor filtering preserves the inductor current slope.
- Current reference matches the rectified line envelope.
- Voltage loop does not modulate the line current shape.
- Switch and diode stress stay inside rating margin.
A model that includes the inductor, current sensor, PWM logic, and compensators will show why some component values look safe on paper and still produce distortion. That is the practical value of SPS SOFTWARE in this workflow: you can test the full CCM boost stage with the sensing and control path attached, then judge parts by the waveform they create. Good PFC design is less about isolated equations and more about keeping every choice honest against current shape.
