Modelling IGBT power devices for converter and drive design

Key Takeaways

• • An IGBT model becomes useful for design when it includes switching loss, diode recovery, gate timing, and the parasitics that shape overshoot and ringing.

  • Model fidelity should match the question you need to answer, from average-value control studies through switched loss checks and electrothermal margin work.

  • Snubber sizing, converter loss estimates, and motor drive stress checks only become trustworthy after the model has been compared with measured switching waveforms.

Accurate IGBT models turn converter design from ideal switching maths into a clear picture of loss, voltage stress, and snubber duty.

That shift matters because power stages fail at switching edges far more often than they fail in the averaged schematic you sketch at the start. Electric motor systems account for nearly 50% of global electricity consumption, so small errors in converter loss and stress assumptions scale into heat, size, and efficiency penalties across a huge installed base. You will get much better design answers when the model includes conduction drop, switching energy, diode recovery, and the parasitics around the package and busbar. That’s the point where simulation stops being a wiring check and starts guiding hardware choices.

Ideal switch models miss the stresses that shape design

An ideal switch model will only answer topology and control questions. It will not tell you how much energy the device burns during turn-on, how high the collector-emitter voltage overshoots, or how the freewheel diode recovers. Those effects set temperature rise, snubber size, and device margin.

A 600 V half bridge feeding an inductive load can look perfectly clean with ideal devices. Add finite tail current, diode reverse recovery, and 20 nH of commutation inductance, and the same leg shows voltage spikes and extra dissipation at every edge. That shifts heat-sink sizing and safe operating margin. It also changes which pulse width modulation pattern looks acceptable.

“You do not need every semiconductor physics detail for every study.”

You do need enough non-ideal behaviour to make the stress picture honest. That usually starts with finite on-state voltage, finite switching time, anti-parallel diode behaviour, and the stray elements around the loop. Once those are present, you’re finally studying the converter you plan to build.

Choose the IGBT model from the study objective

The right IGBT model is the one that answers your present question with believable stress and loss results. Average-value models suit control tuning and power flow studies. Switched models suit gate timing, loss estimation, and snubber work. Detailed electrothermal models suit margin checks near current, voltage, and temperature limits.

A front-end rectifier study rarely needs nanosecond gate-current detail. A double-pulse test model always does. That split is where many projects lose time, because teams either overbuild early models or trust simple ones for device selection. This checkpoint keeps the model scope aligned with the design question.

SPS SOFTWARE fits this workflow because you can start with an editable switched device model and add fidelity where the design question asks for it. You’re not locked into a sealed black box, so assumptions around diode recovery, parasitic inductance, and temperature can be inspected. That transparency helps when a waveform looks wrong and you need to see if the issue is physics or setup. It also keeps teaching and engineering use aligned.

Represent gate control with timing that matches hardware

Gate control must be modelled with the same delays, resistance, and voltage limits that the hardware will use. Dead time, turn-on and turn-off resistance, Miller plateau behaviour, and driver propagation delay all alter current overlap and diode recovery. If those values are generic, the switching waveforms will be generic too.

A phase leg with 200 ns extra turn-on delay in the high-side path will not share current the way an ideal pulse width modulation block suggests. The low-side diode can stay in conduction longer, then recover harder when the upper IGBT takes current. That is why a model with separate source and sink gate resistance gives a better picture than a single rise-time number. You can then see how a smaller turn-off resistor trims tail current yet raises overshoot.

Dead time deserves the same care. Too little dead time risks cross-conduction, and too much shifts loss into the diode and distorts current at light load. Gate timing is not just a control detail. It’s part of the device model because it sets how the device reaches each state.

Capture stray inductance before tuning switching behaviour

Stray inductance decides how violent a switching edge will look once current moves from one commutation path to another. If you tune gate resistance or add a snubber before modelling that inductance, you will tune around the wrong cause. The result is a clean schematic and a noisy prototype.

A practical switched model should include these parasitics before you judge ringing or overshoot.

• The direct current link loop inductance between the capacitor and half bridge
• The emitter sense inductance that feeds back into the gate loop
• The package lead inductance for the IGBT and its anti-parallel diode
• The busbar resistance that damps part of the high-frequency ringing
• The load-side cable capacitance seen during each commutation even

A 30 kW inverter leg shows why this matters. Move the direct current link from an ideal voltage source to a capacitor with loop inductance and equivalent series resistance, and the collector-emitter peak can rise tens of volts on turn-off. That extra peak will alter snubber sizing and can also change your gate-resistor choice. You’re no longer tuning an abstract switch.

Model switching losses with energy tables across temperature

Switching loss modelling should use tabulated turn-on and turn-off energy against current, voltage, gate resistance, and junction temperature. Conduction loss should use on-state voltage or equivalent curves across current and temperature. Those two pieces will give you a credible first-pass loss map for a converter.

A 1200 V device in a pulse width modulated converter rarely switches at the exact datasheet test point. If the data lists turn-on and turn-off energy at 600 V, 300 A, and 125 C, your model should scale or interpolate from that surface instead of assuming one fixed value per transition. Junction temperature then feeds back into the next operating point because hotter silicon switches and conducts differently. That loop exposes cooling margin and overload limits.

Simple overlap formulas still help during early sizing, yet they miss diode reverse recovery, tail current shape, and temperature effects. A loss model that mixes conduction drop with energy tables is more honest and still efficient to run. You can place an averaged thermal block on top of the switched electrical model once the per-pulse energies look believable. That approach keeps the loss estimate tied to the actual commutation event.

Use snubber networks to manage voltage overshoot

Snubber networks manage the voltage and current extremes created by parasitics, and they must be sized against the waveform you actually expect. A snubber that removes overshoot at one load point can waste significant power at another. Good design balances clamp action, damping, and resistor heating.

An RC snubber across a half-bridge switch works well when the main issue is high-frequency ringing from loop inductance and stray capacitance. An RCD clamp suits cases where turn-off overshoot needs a clear path into a storage capacitor and resistor. Each choice shifts stress somewhere else. Lower peak voltage usually comes with higher snubber loss, extra parts, and more thermal duty in the resistor.

Start with the simulated ringing frequency and peak voltage, then tune capacitance to slow the edge seen by the parasitics and resistance to damp the oscillation. A double-pulse setup makes this visible because load current stays controlled while you sweep component values. Snubber design works when it is tied to the commutation loop model. It fails when it’s treated as a patch added after layout choices are fixed.

Apply the same model to motor drive inverters

Motor drive inverter studies need the same IGBT switching model used for converter work, plus the machine, cable, and modulation details that push the device into different operating corners. Motor-driven systems use more than 50% of the electricity consumed in U.S. manufacturing, so loss and stress errors matter at fleet scale as well as bench scale.

A long motor cable can reflect voltage, raise common-mode current, and shift diode recovery stress during pulse width modulation edges. Low-speed high-torque operation adds another twist because phase current stays high while electrical frequency falls. That operating point loads the devices thermally even when the motor feels slow. A model that couples the inverter to the machine and cable will show that mismatch clearly.

Motor drives also expose how average loss numbers can hide local stress. Regenerative braking, step load changes, and field-weakening all move the device through different current and voltage combinations. You’ll want the same loss tables, gate timing, and parasitic network used in converter studies. The only difference is that the load model now has enough detail to push the inverter the way the application will.

Validate simulated switching waveforms against bench measurements early

“A model you can question, tune, and verify will keep your snubber, cooling, and device margin grounded in the same evidence.”

Validation means matching measured and simulated switching waveforms before you trust the model for snubber values, cooling margin, or device selection. Compare collector-emitter voltage, collector current, gate voltage, and ringing frequency from the same test setup. If those shapes line up, the model will guide design work instead of flattering it.

A double-pulse test is the cleanest check because it separates a single turn-on and turn-off event at known current and bus voltage. An inverter leg under pulse width modulation is the next step since dead time and alternating diode recovery enter the picture. Small mismatches are normal around probe bandwidth and package parasitics. Large mismatches usually trace back to missing inductance, wrong gate resistance, or loss scaling from one datasheet point.

Good converter design comes from models that admit loss and stress early enough to change the hardware before drawings harden. That’s why transparent tools matter more than polished ideal blocks. SPS SOFTWARE fits this job when you need inspectable switching models that stay close to the circuit you will build.